A typical BICMOS logic circuit generally comprises two different stages: a first stage consisting of CMOS FETs to achieve the desired logic function; and a second stage, generally comprised of a pair of bipolar transistors to operate as the output driving stage. FETs are used in the first stage to perform the desired logic function because of their superior integration density, low power dissipation and better logic efficiency. Bipolar transistors are utilized in the second, driver stage because of their ability to supply higher currents per unit area. Bipolars therefore require less space than MOSFETs in similar operating conditions and they also exhibit a higher transconductance.
Different schemes exist for utilizing bipolar transistors in BICMOS output stage circuits. For example, U.S. Pat. No. 3,541,353 (Seelbach et al.) discloses an output stage circuit comprised of a top NPN pull-up transistor art a bottom PNP pull-down transistor. According to Seelbach et al., a pair of complementary bipolar transistors are connected in an Emitter Follower (EF) configuration in a manner typical of "Integrated Complementary Logic (ICL)" technology utilized in the BICMOS environment. The two emitters are tied together and the resulting common node is connected to an output terminal. The collectors of the top NPN transistor and the bottom PNP transistor are respectively connected to a positive voltage and to the ground. This version was used early in the art, because all the collectors of NPN transistors are connected to the positive voltage. As a result, collectors are buried and merged, thereby allowing higher possible integration density. In addition, there is no difficulty in manufacturing such a vertical grounded-collector PNP transistor, as will be explained later on. Also, according to this configuration, the influence of the collector-substrate capacitance Ccs is eliminated. However, in the ICL technology, additional biasing means must be connected to the output transistors. This is illustrated in IBM Technical Disclosure Bulletin, Vol. 29, Sept 1986, pp 1857-1858 in an article entitled: "Complementary FET bipolar circuit", by F. Montegari. As depicted in this reference, the extra FET connected between the bases of the bipolar output transistors acts as a voltage shifter for adequate operation. Finally, because the two transistors in the output stage are connected in an Emitter-Follower configuration, the first stage must supply full swing voltage swings, which thereby limits speed performance.
Another version of a bipolar output stage circuit having complementary transistors is disclosed in US U.S. Pat. No. 3,879,619 (Pleshko). This versions consists of top PNP/bottom NPN bipolar transistors. FIG. 1 of the present application shows an electrical schematic in accordance with the teachings of Pleshko. Circuit 10 of FIG. 1 comprises a CMOS logic gate block 11 which performs the logic function, followed by a driving block 12 to operate as the output stage circuit. Block 12 comprises top PNP and bottom NPN bipolar transistors respectively referenced TUP and TDN. Emitters of said transistors are respectively connected to a first supply voltage: a positive voltage (VH) at terminal 13 and a second supply voltage: the ground (GND) at terminal 14. The logic gate block 11 comprises six FETs P1, P2, P3, N1, N2 and N3 connected between VH and GND and driven by logic input signals A1 and A2, applied through terminals 15 and 16 respectively. FETs P3 and N3 are only used for biasing the bases of output transistors TUP and TDN in the quiescent state. The circuit output signal VOUT is available at terminal 17 which is at the same potential as the common output node N formed between the collector regions of output transistors TUP and TDN. The bases of transistors TUP and TDN are driven separately since they are connected to nodes 18 and 19 of logic gate block 11. No voltage shifting means are necessary in this implementation. Circuit 10 depicted in FIG. 1 is a two-input NAND gate, but other circuits performing different logical functions can be built as well. In addition, should the PNP transistor be a high performance transistor, (low collector resistance and a low collector-substrate capacitance Ccs), the BICMOS logic circuit would have excellent speed performances, because both output transistors operate as amplifiers. Moreover, in circuit 10 of FIG. 1, all the FETs can be very small devices because the output transistors need smaller input voltage swings when compared to the former version. For all these reasons, circuit 10 of the complementary inverter type appears very promising.
However, some difficulties are circuit of FIG. 1 is to be integrated with standard BICMOS technologies of the "merged" type, i.e. circuits that combine one bipolar transistor and one FET device (e.g. the NPN transistor P channel FET) in the same well. These technologies usually offer only vertical grounded-collector PNP transistor structures as illustrated in FIG. 2 of the present invention. In the cross-sectional view of FIG. 2, structure 20 comprises both NPN and PNP transistor structures referenced 21 and 22 formed in a P substrate (the respective FET devices have not been shown for sake of simplicity). Structures 21 and 22 are separated by a recessed oxide (ROX) region 24-1. The PNP transistor structure 22 is formed in a low doped P- well 25 embedded in a pocket resulting from the combination of the P+subcollector layer 26 and a P collector reach-through region 27, the latter including a P+collector contact region 27-1. To lower the collector contact resistance, the collector reach-through region 27 is generally U- shaped. The emitter and base regions are respectively referenced 28 and 29. The base region 29 and the collector contact region 27-1 are isolated by a ROX region 24-2. On the other hand, the NPN transistor structure 22 is quite standard and is only briefly detailed hereafter. The NPN structure 21 comprises an N+ emitter region 30 and a P base region 31 formed in a N- well region 32 embedded in a pocket resulting from the combination of a N+ subcollector layer 33 and a N reach-through region 34 provided with a N+ collector contact region 34-1. As apparent from FIG. 2, there are no parasitic devices around the PNP structure Unfortunately though, the structure of FIG. 2 is inadequate when isolated-collector PNP transistor structures are desired. As a matter of fact, because the P substrate 23 is connected to the ground, the P collector region 26/27 of the PNP transistor is also at the potential of the ground.
The manufacturing process used to fabricate the structures illustrated in FIG. 2 may be adapted to build a vertical isolated-collector PNP transistor, taking advantage of the existence of the N+ subcollector layer that is required in the fabrication of the NPN transistor.
A known vertical isolated-collector PNP transistor structure is shown in FIG. 3, and basically consists of a P+ region 36 as the emitter, a portion of the N-epitaxial layer 37 as the base, and the P+ buried subcollector region 38/P+ reach-through region 39 as the collector. This conventional PNP structure 35 is enclosed in a N+ pocket comprised of a N+ buried region 40 in contact with a ring-shaped N+ reach-through region 41 for isolating the collector region 38/39 of the PNP transistor from the P substrate 23. At the surface of the wafer, active regions are separated by appropriate ROX regions 42-1 and 42-2. The PNP transistor structure of FIG. 3 is not fully satisfactory, however, for the following two reasons. First, integration density is reduced due to the loss in silicon area caused by region 40/41. Second, the two highly doped buried regions 38 and 40, that are in intimate contact, generate dislocations that are detrimental to the quality and functionality of the resulting PNP transistor structure 35. This second inconvenience can be avoided by restricting the doping of the buried sub-collector region 40 and reach-through region 41, but not without parasitic devices emerging.
It is to be noted that the manufacturing process of the PNP transistor of FIG. 3 must have specific steps of forming the P+ subcollector region and the P+ reach-through region 39 that are not required to fabricate the NPN transistor structure. However, these extra steps have the great advantage of resulting in a perfectly isolated PNP transistor structure.